Pipeline ADCs are today commonly used for applications requiring 10 to 16 bits resolution at 1 MHz to 100 MHz sample rates, for example for digitising the outputs of CCD or CMOS linear or area image sensors or for digitising analogue video signals. A basic pipeline ADC includes several stages in cascade. Each stage uses a comparator to extract the most significant bit, and then the stage subtracts an analogue signal corresponding to the extracted bit, and amplifies the remaining residue, for use by the next stage. Commonly, more than one bit per stage is extracted, by using multiple comparators. Also, certain arrangements allow over-ranging of the input of each stage to accommodate comparator offsets so that, provided that each stage subtracts an accurate amount and gives an accurate analogue gain, the eventual digital output conversion remains accurate. These ADCs are commonly implemented in CMOS using switched-capacitor technology. However, other techniques, such as switched current, have also been used.
In practice, especially where the input signal amplitude can vary widely, as with an image sensor or communications link, a common implementation has the ADC preceded by an amplifier with controllable gain, termed a Programmable Gain Amplifier (PGA). This gain is often digitally controllable, but may be controlled by other means, such as voltage control or current control in some systems.
The PGA is controlled to amplify or attenuate the input signal so that it is of an amplitude that uses up a substantial proportion (as much as practicable) of the full-scale input range of the ADC. In this way the ADC thermal noise referred to the signal source is proportionately kept as low as possible relative to the signal source, and so its impact is minimised; likewise, the signal presented to the ADC is maximised. Thus, using a PGA, it is possible to make use of the full effective resolution of the ADC.
So as not to degrade the performance of the ADC, the PGA should be at least as linear as the ADC. The PGA should also be operable to settle linearly and quickly into the input impedance of the ADC, and to maintain this settling behaviour over a wide range of programmed gain values. Again, CMOS switched-capacitor technology is often used for this PGA, though alternatives such as op amp circuits using multiple-tapped resistor ladders, or bipolar multiplier cells or other voltage-controlled amplifiers, are also possible.
The PGA op amp can often present greater design challenges than the ADC op amps. It is required to have enough gain-bandwidth to settle accurately in typically half a sample period at maximum gain (say 20 dB or even greater), but has to remain stable when configured with higher feedback factors to give closed loop gain less than unity. It is also necessary for the input-referred noise of the PGA op amp to be low, even when amplifying a small input signal, and the capacitors or resistors around it will be of low impedance to minimise noise. Therefore the operating current will often be as much as all of the amplifiers in the ADC. While the op amps in the ADC also have to settle inside half a sample period, they can be optimised for a fixed closed-loop gain, and will only receive amplified input signals, so can be higher noise and drive higher-impedance circuitry, so power minimisation will be less critical. Also the PGA has to settle to the full resolution of the ADC, whereas the ADC op amps only have to settle to the resolution of the following stage.
For example, for a sample rate of 10 Ms/s, the sample period will be 100 ns. Thus, the PGA will need to settle to within the ADC resolution (say 14 bits) in 50 ns, which is half of this sample period. Assuming a single-pole settling model, this implies settling to 10 time constants in 50 ns, i.e. with a time constant of 5 ns, or a closed-loop bandwidth of 30 MHz. If the PGA is set to a gain of 10, this thus requires an op amp with open-loop gain-bandwidth of approximately 300 MHz, but stable at closed loop gain <<1.
In practice, allowing for clock under-lap, the available settling time may be less than 50 ns, and slewing, clock injection effects, or other second-order effects may require an even faster op amp.
This is inherently more difficult to achieve than in an ADC, which has a closed loop gain of, for example, 2, thus requiring a gain bandwidth of 60 MHz and only needing to be stable for constant gain A=2.
An n-bit pipeline ADC extracting one bit per stage requires n separate stages, each including an op amp, comparators, and a switched-capacitor array. This uses significant silicon area, each stage adding to die cost, but these ADCs are often required in high-volume consumer equipment, where manufacturing cost is very important. Also each stage consumes power, whereas many applications such as Digital Cameras are battery-powered portable equipment, so low power is important. Pipeline ADCs extracting more than one bit per stage have fewer stages, but each is more complex, consuming more area and more power per stage, so the net saving in terms of power and area is limited.
Thus, it would be desirable to obtain the performance of a pipeline ADC, with improved use of the active area of a solid state device. It would further be desirable to obtain the performance of a pipeline ADC with improved power consumption.
In the event that improved use of active area of a solid state device can be achieved, with improved power consumption, it could, in certain circumstances, be desirable to sacrifice this improvement in these performance criteria to the benefit of improved performance in terms of other performance criteria, such as noise, resolution and/or linearity.
For a given manufacturing technology, there comes a performance threshold at which it becomes increasingly difficult for a designer to get higher speed or better performance, without consuming a lot of extra power or requiring complicated and area-consuming topologies or requiring exceptional skill and the invention of novel circuit techniques. However, using common 0.35 μm CMOS, it is quite possible for a person reasonably skilled in the art to design an op amp capable of use in implementing an ADC operating up to 30 Ms/s at (say) 12 bits resolution, without hitting this performance threshold.
For applications at lower sample rates, say 3 Ms/s, one possibility is to use the same comfortably designed 30 Ms/s amplifier in successive 30 Ms/s clock cycles to implement the processing of successive stages, rather than dedicating an amplifier to each stage, just operating at 3 Ms/s. This results in a circuit architecture similar to cyclic (also termed recirculating, or algorithmic) ADCs. For a given sample rate, this requires faster settling, since all the processing for n stages needs to be squeezed into one sample clock cycle. The main problem is that the PGA now has to drive the input capacitors in a small fraction of the 3 Ms/s sample rate.
Examples of circuit designs comparable with specific embodiments from the state of the art will now be described, with discussion of their features, operation and certain disadvantages.
FIG. 1a shows a switched-capacitor PGA 10 driving a 1-bit per stage switched-capacitor pipeline ADC 20, extracting 1 bit per stage. One stage 22 of the pipeline ADC is illustrated in detail, and a second stage schematically, it being understood that further stages are to be added to the output to this stage until the desired resolution is reached.
The switched capacitor PGA 10 comprises an op amp 12 whose non-inverting input is tied to ground. One terminal of a variable input capacitance Ca1 is connected to an input on which an input signal Vin is received in use, via a switch Sw1. Another switch Sw3 lies between the same end of the input capacitance Ca1 and ground. A further switch Sw4 connects the other terminal of the input capacitance Ca1 to ground, and a further switch Sw2 connects that latter terminal to the inverting input of the op amp 12.
In use, switches Sw1 and Sw4 close on receipt of a clock signal φ1, as marked, and switches Sw2 and Sw3 close on receipt of another clock signal φ2.
The system is driven by these two-phase, non-overlapping clocks φ1, φ2, whose timing diagrams are illustrated in FIG. 1b. Because the clocks are non-overlapping, actions dependent on one of the clock signals being high are completed before actions dependent on the other of the clock signals being high, as the two clock signals are never simultaneously high. For convenience in the following description, the phase wherein φ1 is high is expressed as ‘phase φ1’ and the phase wherein φ2 is high is similarly expressed as ‘phase φ2’.
A second feedback capacitance Ca2 is connected between the output of the op amp 12 and the inverting input and a switch Sw5, which also closes in phase φ1, is connected across this feedback capacitance Ca2.
The illustrated first stage 22 of a pipeline ADC 20 comprises a further op amp 24, whose non-inverting input is tied to ground. The stage also comprises first and second input capacitors C1a and C1b respectively, and a flash ADC 26 and a DAC 28 in the usual manner. The flash ADC compares its input against one or more reference levels, which may include ground. It may be regarded as a set of one or more comparators. The output of the flash ADC 26 is connected to the input of the DAC 28 and also comprises the output of the bit extracted from the ADC stage 22. The output of the DAC 28 feeds back, via a switch Sw9, which switches in phase φ1, to one end of the first input capacitor C1a. The same end of the first input capacitor is connected, via a switch Sw8, which switches in phase 42, to the input to the stage 22, which receives a signal Vsig output from the input PGA 10.
One terminal of the other input capacitor C1b is connected, via a phase φ2 switch Sw7, to the same input of the stage 22. That terminal is also connected, via a further phase φ1 switch Sw6, to the output of the op amp 24.
The other terminal of the first input capacitor C1a is connected, via a phase φ2 switch Sw13, to ground, and, via another phase φ1 switch Sw12, to the inverting input of the op amp 24. Similarly, the other terminal of the second input capacitor C1b is connected, via a phase φ2 switch Sw11, to ground, and, via another phase φ1 switch Sw10, to the inverting input of the op amp 24.
The inverting input is further connected to the output of the op amp 24, via a phase φ2 switch Sw14; the stage input Vsig feeds into the flash ADC 26 via another phase φ2 switch Sw15. In this example, this is a 1-bit flash ADC, functionally equivalent to a simple comparator, which senses whether the input voltage Vsig is greater or less than ground. Its digital output drives a DAC 28, in this case a simple 1-bit DAC, delivering a conversion result signal or voltage Vdac equal to +Vref or −Vref depending on the polarity of Vsig.
With reference to the timing diagram of FIG. 1b, switches Sw1, Sw4 and Sw5 of the PGA are driven closed by the first clock signal φ1. Switches Sw2 and Sw3 are driven closed by the second clock signal 42, as illustrated in FIG. 1a. 
Operation of the input PGA will now be described. In phase φ1, input capacitance Ca1 is charged between Vin and ground by closing switches Sw1 and Sw4 as shown. Meanwhile capacitance Ca2 is discharged by the closed switch Sw5 across its terminals, and the op amp inverting input is driven to a virtual earth by the op amp 12 via the short circuit formed by this switch Sw5.
In the other phase φ2, when the phase φ1 switches are open, the input side of Ca1 is grounded by closing the appropriate switches Sw2 and Sw3, and the op amp forces the other end of Ca1 (connected thereto by the closing of the phase φ2 switch Sw2) to virtual ground by passing its charge onto Ca2. By charge conservation on the common node of Ca1 and Ca2, the op amp output Vsig=(Ca1/Ca2)*Vin. The gain of the PGA 10 is programmed by varying Ca1 and Ca2—in a practical implementation each of these would usually be implemented by banks of parallel capacitors selected by CMOS switches.
Operation of stage 1 of the ADC will now be described. In phase φ2, the op amp 12 of the input PGA also charges up the ADC input capacitors C1a, C1b to Vsig via the phase φ2 switches Sw7, Sw11, Sw8 and Sw13. This is the familiar sampling step of pipeline ADCs.
In stage 1 of the ADC, during phase φ2, the op amp 24 is reset by switch sw14 to discharge parasitics on its inverting input to ground.
Then, switches Sw7, Sw11, Sw8, Sw13 and Sw14, previously closed, are opened, retaining Vsig stored on capacitors C1a and C1b. This is the ‘hold’ step, and thus this arrangement is the familiar ‘sample and hold’ aspect of the ADC.
In the next phase 1, the Vsig end of C1a is switched to Vdac by means of the phase φ1 switch Sw9, and the Vsig end of C1b is connected to the op amp output Vout1 by means of the corresponding phase φ1 switch Sw6. The other ends of these capacitors are connected to the virtual earth created at the op amp inverting input via switches Sw10 and Sw12 respectively.
The total charge on the plates of C1a and C1b opposite from those connectable to the stage input is thus Vdac*C1a+Vout1*C1b. However the total charge on these plates at the end of the previous phase φ2 is Vsig*(C1a+C1b). Equating these charges gives:Vdac*C1a+Vout1*C1b=Vsig*(C1a+C1b)
In this example C1a is selected to be equal to C1b, so:Vdac+Vout1=2*VsigSoVout1=2*Vsig−VdacFor example, if Vsig=+Vref, then Vdac=+Vref, and Vout1=+Vref.If Vsig=+10 mV, then Vdac=+Vref, so Vout1=20 mV−Vref.If Vsig=−10 mV, then Vdac=−Vref, so Vout1=−20 mV+Vref.
The transfer characteristic is shown in FIG. 2a. This residue signal 2*(Vsig+/−Vref/2) charges up the input capacitors of the ADC second stage in φ1, ready to give its output in turn at the next phase φ2.
This arrangement has the disadvantage that, unless the input offset of the flash ADC comparator is less than 1LSB (for 14 bits, Vref=1V, 1LSB=1V/16384=60 μV, which is impractical in terms of offset voltage and overdrive required for reasonable response time), the extreme outputs of stage 1 will exceed or not get to the full-scale input range of the subsequent processing, so the whole pipeline ADC will exhibit missing or duplicate codes as the input is swept over the signal range. The effect of this on the transfer characteristic is illustrated in FIG. 2b. 
To avoid this, a well-known modification to this arrangement replaces the single comparator in the flash ADC 26 by a pair of comparators with thresholds +/−(Vref/2), which can be regarded as a two-threshold comparator, and the two-level DAC by a three-level DAC with three possible conversion results or outputs:Vdac={−Vref, 0, +Vref}.
The transfer function for this modification is illustrated in FIG. 2c. If there is a comparator error, the output of the corresponding pipeline stage will exceed +/−Vref, but since the useful input range of the following stage is now extended past +/−Vref, this merely alters the codes generated downstream to compensate, and so reasonable errors in the comparators can be corrected for. This technique is known as the Digital Error Correction (DEC). DEC also relaxes the comparator input overdrive specification, since there is a wide band of “don't care” levels for the comparator, for instance +/−(Vref/10) or 100 mV, rather than 1LSB or 60 μV. Thus, a simple comparator is adequate yet will still react swiftly to the larger overdrive, and so can be designed to sample the input almost at the end of φ2, and be ready to drive the DAC at the start of non-overlapping clock φ1, thereby allowing the PGA op amp (or the ADC op amp, in the case of later stages of a multi-stage converter) the maximum time to settle, i.e. almost half of the input signal sample period.
A further modification, as mentioned above, is to extract two or more bits per stage, using a higher-resolution flash ADC (or multi-threshold comparator) and DAC giving fewer, but more complex stages, and thus introducing an extra degree of freedom in the optimisation of power, area and performance. To illustrate this variant, FIG. 3 shows an ADC stage comprising a capacitor bank structure 40 for extracting 2 bits per stage.
In the capacitor bank structure, five capacitors C1a, C1b, C1c, C1d and C1e are provided. A first terminal of each of four of the capacitors (C1a through C1d) is connected to Vdac via a switch (Sw29, Sw26, Sw25, Sw22 respectively) closed in a first clock phase φ1. The same terminal of each of the said four capacitors (C1a though C1d) is connected to Vsig via a switch (Sw28, Sw27, Sw24, Sw23 respectively) closed in a second clock phase φ2.
The other terminal of each of the said four capacitors is connected to the inverting input of the op amp 24, as is a terminal of the fifth capacitor C1e, each via a respective switch (Sw39, Sw36, Sw35, Sw32, Sw30) closed in the first clock phase φ1. Said five capacitor terminals are also connected to ground via respective switches (Sw38, Sw37, Sw34, Sw33, Sw31) closed in the second clock phase φ2.
The opposite terminal of the fifth capacitor C1e is connected to the output of the op amp 24 via a switch Sw20 closed in the first clock phase φ1. That output is also connected to ground, via a switch Sw21 closed in the second clock phase φ2.
A reset switch Sw40 is connected across the output and the inverting input of the op amp, closed during a reset phase φR.
The stage input Vsig feeds into the flash ADC via another phase φ2 switch Sw41, whose digital output drives a DAC, delivering a conversion result signal or voltage Vdac.
In this example, the flash ADC levels are −¾*Vref, −¼*Vref, +¼*Vref, and +¾*Vref, and the capacitor array consists of 4 equal input capacitors C1a, C1b, C1c, C1d, and a fifth capacitor C1e, which is thus grounded in the first clock phase φ2, then switched in feedback in the alternate clock phase φ1, while the input capacitors are connected to the DAC, whose output is one of {−Vref, −Vref/2, 0, +Vref/2, +Vref}.
The DAC illustrated in FIG. 3 may comprise a resistor potential divider to generate these levels. Alternatively, to avoid this potential divider, the switching of C1a, C1b, C1c, C1d in phase φ1 may be modified by adding extra switches controlled by the DAC control word, to switch them to +Vref and −Vref in combinations of (4,0) (3,1) (2,2) (1,3) (0,4) to generate net charge corresponding to −Vref, −Vref/2, 0, +Vref/2, and +Vref (i.e. −Vref*Ctot, −Vref/2*Ctot, . . . , where Ctot=C1a+C1b+C1c+C1d) according to the DAC control word. These switches may either be extra series switches directly controlled by the DAC control word, or may be the switches Sw29 etc. as shown, connected directly between +/−Vref and the respective capacitors, but controlled by bits derived from the DAC word and gated with the appropriate clock phase.
Whereas the examples described above, with reference to FIGS. 1 to 3, all rely on the provision of several stages to construct an ADC of desired resolution, it would be advantageous to reduce the number of op amps and capacitor banks to reduce chip area and total power consumption, especially for desired sample rates well within the speed capabilities of the technology.
“Efficient Circuit Configurations for Algorithmic Analog to Digital Converters” (K. Nagaraj, IEEE Trans. on Circuits and Systems II vol. 40 No. 12 Dec. 1993) describes a recirculating ADC arrangement in which banks of capacitors are used to store residual voltages, for re-presentation to conversion means.
FIG. 4 shows a similar arrangement, providing the same simple function as the ADC 20 illustrated in FIG. 1, but using only one amplifier and flash ADC. The schematic is similar to FIG. 1, but a second capacitor bank C2a, C2b is added.
Thus, as illustrated in FIG. 4, the output of the DAC 28 feeds back, via switch Sw59, which switches in phase φ1, to one end of the first input capacitor C1a. The same end of the first input capacitor is connected, via a switch Sw58, which switches in phase φ2, to a node A connected to the input to the stage 22 (which receives a signal Vsig output from the input PGA 10) via a switch Sw51 closed in a sub-phase φ2x of the phase φ2, and to the output of the op amp 24 via a switch Sw50 closed in a sub-phase φ2y of the phase φ2.
One terminal of the other input capacitor C1b in that bank is connected, via a phase φ2 switch Sw57, to the same node A of the stage 22. That terminal is also connected, via a further phase φ1 switch Sw56, to the output of the op amp 24.
The other terminal of the first input capacitor C1a is connected, via a phase φ2 switch Sw68, to ground, and, via another phase φ1 switch Sw69, to the inverting input of the op amp 24. Similarly, the other terminal of the second input capacitor C1b is connected, via a phase φ2 switch Sw67, to ground, and, via another phase φ1 switch Sw66, to the inverting input of the op amp 24.
The other capacitor bank C2a, C2b is clocked in anti-phase to the original ADC input bank C1a, C1b. This arises because the output of the DAC 28 feeds back, via switch Sw55, which switches in phase φ2y, to one end of the first input capacitor C2a of that bank. The same end of the first input capacitor C2a is connected, via a switch Sw54, which switches in phase φ1, to the output of the op amp 24.
One terminal of the other input capacitor C2b in that bank is connected, via a phase φ1 switch Sw53, to the output of the op amp 24. That terminal is also connected, via a further phase φ2y switch Sw52, to the output of the op amp 24.
The other terminal of the first input capacitor C2a is connected, via a phase φ1 switch Sw64, to ground, and, via another phase φ2y switch Sw65, to the inverting input of the op amp 24. Similarly, the other terminal of the second input capacitor C2b is connected, via a phase φ1 switch Sw63, to ground, and, via another phase φ2y switch Sw62, to the inverting input of the op amp 24.
A switch Sw60 presents the voltage at node A to the Flash ADC 26 in phase φ2 while, in phase φ1, the voltage on the output of the op amp is presented to the Flash ADC 26, by means of a switch Sw61.
A reset switch Sw70 across the op amp is also provided.
FIG. 5a shows a suitable clocking scheme, here illustrating only a 6-bit conversion for simplicity.
The underlying principle of operation is that capacitors C2a, C2b sample the output of the op amp in one phase, this output being based on the charge currently on C1b resulting from charge on C1a corresponding to the DAC output or conversion result signal Vdac and charge previously on C1a and C1b due to the previous op amp output. Then, in the next phase, C1a, C1b sample the op amp output based on the previous op amp output stored on C2a, C2b and the updated Vdac. This continues in a recirculating manner until the required degree of resolution has been reached.
Operation of the arrangement of FIG. 4 will now be described, with reference to FIG. 5a which shows a suitable clocking scheme.    a) In a first phase (φ2x) of the conversion cycle, Vsig charges up C1a and C1b, via an additional switch Sw51 interposed on the stage input. The flash ADC samples this Vsig, and latches its output for later use by the DAC. At the end of this phase, C1a, C1b are disconnected, to store the sampled Vsig.    b) Then, the op amp is reset by φR. For this first phase, this action could be performed simultaneously with the above φ2x phase, since the op amp output is not used, but on subsequent phases, this would short out a desired op amp output. Thus, in the illustrated example, phase φR comprises a signal which, for all cycles, closes the reset switch after completion of each of phases φ1, φ2x, and φ2y, as illustrated in FIG. 5a.     c) In the next phase, φ1, a residue 2*(Vsig+/−Vref/2) appears on the op amp output. This arises in a similar way to that described in relation to FIG. 1, with C1b acting as a feedback capacitor and C1a driven by the DAC, itself driven by the previously latched flash ADC output. The flash ADC samples the op amp output signal, and again latches its output for later use by the DAC. The op amp output is fed round to charge C2a and C2b. Then all capacitors are isolated again at the end of this phase.    d) Then the op amp is reset (by closing switch φR), ready for the next phase.    e) In the next phase φ2y, C2b acts as a feedback capacitor, C2a is driven by the DAC according to the previous flash ADC output, and the op amp delivers the next residue to C1a, C1b via switch Sw50 (with the Vsig switch sw51, closed in φ2x, being open in this phase).    f) Then, again, the op amp is reset (φR), ready for the next phase φ1.    g) In the next phase φ1, configured as (b), the next residue appears at the op amp, and is fed back to C2a, C2b. The cycle then continues from (d) until a desired number of bits is extracted.    h) Once the desired number of bits has been extracted, the entire process is restarted from step (a) with a new sample of Vsig.
The cycle described above with regard to FIG. 4 includes a reset every phase, analogous to the op amp reset in FIG. 1. However it is not necessary to reset every cycle. In an ideal implementation of this embodiment, it will be understood that it is only necessary to reset the op amp at the very start of operation, for example on power-up, since the op amp inverting input will settle back to very close to virtual earth voltage before the end of each phase, at which time the capacitors on that node are disconnected, leaving the inverting input voltage unchanged, still at the voltage to which it was reset, and hence not requiring further resetting.
However, incomplete settling of the op amp, in conjunction with parasitic capacitances on that node, may lead to some residual virtual earth signal charge propagating from one phase to the next. Assuming settling to less than 1LSB at the output, and parasitic capacitances smaller than the signal capacitances, this effect will be negligible during a few conversions, but over thousands of conversions the resulting errors might accumulate. Also, there is the possibility of other second-order effects, such as some pumping of charge by switch clock feed-through. Further, there will be some small but non-zero leakage currents associated with real switches on this node.
Therefore, it is typically convenient to reset once every complete conversion, during clock phase φ2x, in which case the clocking arrangement of FIG. 5b is possible, giving almost a complete half-sample-period for each phase rather than only a quarter-sample-period. For a conversion of N bits, N/2 clock cycles are required. So, a 12-bit 5 Ms/s converter would require a clock of 6×5 Ms/s=30 Ms/s, and op amp settling in less than 1/(2*30 Ms/s)=16.7 ns, the same as a more conventional 30 Ms/s multi-stage pipeline converter.
It will be appreciated that the comparators in the flash ADC need to sample every half-cycle. Typically such a flash ADC will contain clocked comparators, which need a reset phase before each cycle. It would be possible to use two flash ADCs in parallel, resetting each on alternate phases. Alternatively, and preferably, given that the ADC will respond with adequate accuracy very quickly as discussed above, ADC clocks, shown as φRS, can be introduced. The flash ADC is then reset when φRS is low, it is operable to sample at the rising edge of φRS, and to latch data into the DAC control word on the falling edge of φRS. Clock φRS rises at or shortly before the falling edge of φ2 and falls at or shortly before the rising edge of φ1.
It is noted that the above scheme can be readily extended to allow comparator offset correction, by DEC as described above, by setting the flash ADC comparator levels to +/−Vref/2 and Vdac to {−Vref, 0, Vref}.
In the arrangement of FIG. 4, the preceding PGA still only has the width of φ2x (16.7 ns in this example), to settle into the ADC input capacitors. As discussed above, it is desirable to maximise the time available for the PGA amplifier to settle, to reduce its required gain-bandwidth requirement and hence its area and power requirements.
Some improvement could be obtained by stretching the on-time of the initial phase comprising φ2x but, for a given input sample rate, this implies decreasing the time for the remaining conversion phases, so only limited improvement is available without reducing the available settling time for the later stages to well below 16.7 ns.